The present disclosure relates generally to computer system clocking, and, in particular, to a digital frequency locked loop for multi-frequency clocking in a multi-core processor system.
Existing clock distribution trees are impractical to design, fabricate and yield for microprocessors including a large numbers of processing cores in newly emerging multi-core micro-architectures which are increasing processor speed to gain additional performance. Complementary metal oxide semiconductor (CMOS) gate-leakage power or passive power is increasingly dominating power dissipation in fast microelectronic circuits on chips made in 65 nm technology and smaller lithography. Reduction of heat is a major industry concern, and, begins with microprocessor chips in computer systems, such as servers populating data centers. Controlling operating frequencies of individual microprocessor cores and chips can reduce overall power consumption and heat dissipation while optimizing performance. Typical computer system clocking schemes utilize a master oscillator to generate a system clock signal, which is distributed as a clock tree. As the number of processing cores in multi-core processing systems continues to grow, it would be beneficial to minimize clock tree lines and replace high speed clock distribution nets with local core clocking.
In distributing and stepping up or down clock signals, some computer systems employ one or more phase locked loops (PLLs). PLLs typically operate on a feedback loop mechanism that attempts to minimize the phase difference between the reference signal and the scaled clock signal, thereby phase aligning the two signals. While PLLs can be effective, they have a number of shortcomings. For example, a PLL can lock onto harmonics of the reference clock frequency, rather than the reference clock frequency itself. PLLs can suffer from common phase-noise and susceptibility to jitter and skew, known as “skitter”. Capture, lock, and voltage fluctuations may destabilize PLLs. Additionally, PLLs typically rely on a single point solution, where a control circuit attempts to drive phase-error to a null or zero value, which can increase the chance of a false lock while also requiring a continuous reference clock to maintain a lock and generate an output clock. Therefore, it would be beneficial to develop an approach to perform multi-frequency clocking in a computer system that supports a variety of frequencies while avoiding issues associated with PLLs. Accordingly, there is a need in the art for a digital frequency-locked loop to generate a stable local core clock for multi-core processors.